1. Technical Field
The present disclosure relates to data propagation within a data transmission network. The present disclosure applies in particular to SOCs (Systems On Chip) comprising at least one node, two data links managed in accordance with at least one data transmission protocol.
2. Description of the Related Art
SOCs increasingly tend to gather into a same integrated circuit hardware components such as heterogeneous processor cores, specialized circuits, and memories, as well as a complex communication architecture called “network on chip” NOC, linking the components between them. A network on chip usually comprises several point-point data links linking the hardware components of the system on chip. The data links between the hardware components of a system on chip may be made using buses complying with several protocols such as STBus and VSTNOC of the company STMicroelectronics, AXI and AHB of the company ARM, OCP of the company SONICS, DTL and MTL of the company NXP, and Danube of the company ARTERIS. Such a network may carry data of different natures while respecting different carrying constraints. Thus, data of the voice or sound type generally require a low latency and a relatively low bandwidth. Data of the video sequence type also generally require a low latency, but also a high bandwidth. On the other hand, carrying ordinary data does not generally require a high latency, and a variable bandwidth. A certain quality of service is desired whatever the type of data.
Due to the increasing complexity of systems on chip, it is desirable to implement designing, modeling and simulation tools allowing a system to be tested at different designing steps, so as to be able to validate the system at each step. It is also desirable to be able to test a system once it is totally or partially implemented into an integrated circuit.
Generally, developing a complex system such as a system on chip starts with a step of defining specifications written in informal language. Then, there is a step of defining or selecting algorithms to match the specifications. The algorithms may be defined using a high level language like Matlab or C++. Defining the algorithms makes it possible to pass to a step of defining models of a first level of abstraction called “Transaction Level Model” TLM describing an architecture and therefore specifying a distribution between hardware and software (definition of the hardware components and software executed by the hardware components). The Transaction Level Model may gather functional models PV (Programmer View) and timed models PVT (Programmer View+Timing). A functional model makes it possible for example to simulate software embedded in a hardware component of the system. In a functional model, data transfers between the hardware components may be simulated by an ideal unique communication channel, i.e., having a not limited rate. Timed models make it possible to precociously evaluate a choice of architecture and distribution of processes between hardware and software. In order to specify the time constraints that the hardware components of the system will have to respect, the size of the words and the rate of the communication channels may be fixed. A Transaction Level Model may be defined using a language for modeling hardware systems such as SystemC, making it possible to represent hardware components by modules which are linked between them by ports connected to communication channels. The behaviors of hardware and software components are described by processes executing code in a programming language such as C++. All the hardware and software components of a system may thus be modeled using SystemC, whatever the nature and the abstraction level thereof. The following development step consists in adding the clock concept to create a model with the precision of the BCA (Bus Cycle Accurate) cycle specifying the behavior of the system at each cycle of a clock clocking the system. Then there is the step for defining the Register Transfer Level RTL which then allows an integrated circuit to be rapidly and efficiently synthesized. The level RTL defines the value of each bit at each clock pulse using a language such as VHDL or Verilog. The level RTL then makes it possible to define logic gate networks which may be processed by placement and routing tools to obtain a two-dimension structure which serves as a base to make masks for manufacturing the integrated circuit.